1. Field of the Invention
The present invention relates to a voltage level converter circuit that is provided inside a semiconductor integrated circuit device which operates at a plurality of different power source voltages.
2. Description of the Related Art
Advances are being made in the lowering of the power source voltage in order to achieve low power consumption in semiconductor integrated circuit devices, and particularly in the CMOS type semiconductor integrated circuit device. For example, an external circuit which supplies signals to a semiconductor integrated circuit device which is driven by a low voltage such as 0.9V to 1.1V is driven by a 3.0V to 3.6V power source voltage for example. In the case where the value of the power source voltage for the semiconductor integrated circuit device is different from that of the external circuit which drives the semiconductor integrated circuit device, a voltage level converter circuit which converts voltage level is provided in the semiconductor integrated circuit device in order to achieve an interface with the external circuit.
The voltage level converter circuit described in FIG. 2B of Jpn. Pat. Appln. KOKAI Publication No. 11-195975 has been conventionally known as this type of voltage level converter circuit. The voltage level converter circuit described in the publication includes a pair of complementary circuits including a NMOS transistor and a PMOS transistor, and low voltage level signal is supplied to each gate terminal of the pair of NMOS transistors, and high level signal in which the voltage has been increased is output via one PMOS transistor.
In the above-described conventional circuit, when the switch is made from the state in which high level signal is output via the PMOS transistor, to that where the next NMOS transistor is in an ON state and low level signal is output in one complementary circuit, the time until the PMOS transistor and the NMOS transistor are simultaneously in the ON state is long and the transfer time of the output signal from high level to low level is also long.
In order to solve this problem, in the voltage level converter circuit shown in FIG. 3 of the above-described publication, the current brocking PMOS transistor is serially connected to each of the PMOS transistors in the pair of complementary circuits.
However, in the voltage level converter circuit, when the low voltage level signal that is supplied to the gate terminal of the NMOS transistor is lowered, the ON resistance is reduced and thus the transition time when the output signal changes from high level to low level can not be improved by being decreased.